module top(rst, clk, hex1, hex2);
  input rst;
  input clk;
  output [6:0] hex1;
  output [6:0] hex2;

  wire [7:0] out;

  lfsr lfsr1(rst, clk, out);
  bcd7seg bcd7seg1(out[3:0], hex1);
  bcd7seg bcd7seg2(out[7:4], hex2);

endmodule
